ADM1068 datasheet(13/28 Pages) AD

13 / 28 page

Preliminary Technical Data

ADM1068

Rev. PrB | Page 13 of 28

VXn PINS AS DIGITAL INPUTS

As mentioned previously, the VXn input pins on the ADM1068

have dual functionality. The second function is as a digital input

to the device. Therefore, the ADM1068 can be configured for up

to four digital inputs. These inputs are TTL/CMOS-compatible.

Standard logic signals can be applied to the pins: RESET from

reset generators, PWRGOOD signals, fault flags, manual resets,

and so on. These signals are available as inputs to the SE, and

can be used to control the status of the PDOs. The inputs can be

configured to detect either a change in level or an edge.

When configured for level detection, the output of the digital

block is a buffered version of the input. When configured for

edge detection, once the logic transition is detected, a pulse of

programmable width is output from the digital block. The width

is programmable from 0 µs to 100 µs.

The digital blocks feature the same glitch filter function that is

available on the SFDs. This enables the user to ignore spurious

transitions on the inputs. For example, the filter can be used to

debounce a manual reset switch.

When configured as digital inputs, each of the VXn pins has a

weak (10 µA) pull-down current source available for placing the

input in a known condition, even if left floating. The current

source, if selected, weakly pulls the input to GND.

DETECTOR

VXn

(DIGITAL INPUT)

GLITCH

FILTER

VREF = 1.4V

SEQUENCING

ENGINE

–

Figure 17. VXn Digital Input Function

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