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ICS93701 Fiches technique(PDF) 5 Page - Integrated Circuit Systems

No de pièce ICS93701
Description  DDR Phase Lock Loop Clock Driver
PDF  9 Pages
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Fabricant  ICST [Integrated Circuit Systems]
Site Internet  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS93701 Fiches technique(HTML) 5 Page - Integrated Circuit Systems

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ICS93701
0417B—10/29/02
Recommended Operating Condition (see note1)
TA = 0 - 85
oC; Supply Voltage A
VDD, VDD = 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDDQ, AVDD
2.3
2.5
2.7
VDDI2C
2.3
3.6
V
VIL
-0.3
0
VDD-0.4
V
VIH
0.4
0.71
VDD+0.3
V
DC - CLKT, FB_INT
0.36
VDDQ +0.6
V
AC - CLKT, FB_INT
0.5
VDDQ +0.6
V
Output differential crossing
voltage
VOX
VDDQ/2 -0.2
1.25
VDDQ/2 +0.2
V
1 Differential input signal voltage specifies the differential voltage [V
TR - VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
Input voltage level
Analog/core Supply
Voltage
Input differential-pair
voltage swing
1
VID
V
Input differential crossing
voltage
VIX
0.45x(VIH-VIL)0.55x(VIH-VIL)
Timing Requirements
TA = 0 - 85
oC; Supply Voltage A
VDD, VDD = 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
33
270
MHz
Application Frequency Range
freqApp
2.5V+0.2V @ 25
oC
60
170
MHz
Input clock duty cycle
dtin
40
60
%
from VDD = 3.3V to 1%
target freq.
100
µs
CLK stabilization
TSTAB



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