DF2S5M4FS

2

5.

5.

5.

5. Example of Circuit Diagram

Example of Circuit Diagram

Example of Circuit Diagram

Example of Circuit Diagram

6.

6.

6.

6. Quick Reference Data

Quick Reference Data

Quick Reference Data

Quick Reference Data

Characteristics

Working peak reverse voltage

Total capacitance

Dynamic resistance

Electrostatic discharge voltage

(ISO10605) (Contact)

Symbol

VRWM

Ct

RDYN

VESD

Note

(Note 1)

(Note 2)

(Note 3)

Test Condition



VR = 0 V, f = 1 MHz





Min









Typ.



0.45

0.35



Max

3.6

0.55



30

Unit

V

pF

Ω

kV

Note 1: Recommended operating condition.

Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of

dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A.

Note 3: Criterion: No damage to devices.

6.1.

6.1.

6.1.

6.1. ESD Clamp Waveform (Note)

ESD Clamp Waveform (Note)

ESD Clamp Waveform (Note)

ESD Clamp Waveform (Note)

Fig.

Fig.

Fig.

Fig. 6.1.1

6.1.1

6.1.1

6.1.1 +8 kV

+8 kV

+8 kV

+8 kV

Fig.

Fig.

Fig.

Fig. 6.1.2

6.1.2

6.1.2

6.1.2 -8 kV

-8 kV

-8 kV

-8 kV

Fig.

Fig.

Fig.

Fig. 6.1.3

6.1.3

6.1.3

6.1.3 IEC61000-4-2 (Contact)

IEC61000-4-2 (Contact)

IEC61000-4-2 (Contact)

IEC61000-4-2 (Contact)

Note:

The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2019-11-01

Rev.2.0

©2019

Toshiba Electronic Devices & Storage Corporation