SPC58EG80C3 datasheet(122/139 Pages) STMICROELECTRONICS

122 / 139 page

Package information

SPC584Gx, SPC58EGx, SPC58NGx

122/139

DS11758 Rev 6

5.4.3

FPBGA292

5.4.4

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 1

TJ = TA + (RθJA * PD)

where:

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards

to provide consistent values for estimations and comparisons. The differences between the

values determined for the single-layer (1s) board compared to a four-layer board that has

two signal layers, a power and a ground plane (2s2p), demonstrate that the effective

thermal resistance is not a constant. The thermal resistance depends on the:

•

Construction of the application board (number of planes)

•

Effective size of the board which cools the component

•

Quality of the thermal and electrical connections to the planes

•

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using

fewer vias to connect the package to the planes reduces the thermal performance. Thinner

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation

without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

Table 72. Thermal characteristics for 292-pin FPBGA

Symbol

Parameter(1)

Conditions

Value

Unit

RθJA

D Junction-to-Ambient, Natural Convection (2) Four layer board (2s2p)

21.3

°C/W

RθJB

Junction-to-board(3)

—9.8

°C/W

RθJC

Junction-to-case(4)

—6.5

°C/W

ΨJT

Junction-to-package top(5)

Natural convection

0.6

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

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