WM8770SIFT datasheet(9/52 Pages) WOLFSON

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Production Data

WM8770

PD Rev 4.1 June 2005

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless

otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

tMCLKH

MCLK System clock pulse width low

tMCLKL

MCLK System clock cycle time

tMCLKY

1000

MCLK Duty cycle

40:60

60:40

Power-saving mode activated

After MCLK stopped

µs

Normal mode resumed

After MCLK re-started

0.5

MCLK

cycle

Table 1 Master Clock Timing Requirements

Note: If MCLK period is longer than maximum specified above, DACs are powered down with internal digital audio filters

being reset. In this mode, all registers will retain their values and can be accessed in the normal manner through the

control interface. Once MCLK is restored, the DACs are automatically powered up.

DIGITAL AUDIO INTERFACE – MASTER MODE

Figure 2 Audio Interface - Master Mode

BCLK

DOUT

ADCLRC

DIN1/2/3/4

DACLRC

WM8770

CODEC

DSP/

ENCODER/

DECODER

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