STA8090GA datasheet(16/32 Pages) STMICROELECTRONICS

16 / 32 page

General description

STA8090GA

16/32

DS10820 Rev 5

UART features

The UARTx (x = 1|2) are Universal Asynchronous Receiver/Transmitter that support much

of the functionality of the industry-standard 16C650 UART. The main features are:



Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),

or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate

generator



5, 6, 7 or 8 bits of data



Even, odd, stick or no-parity bit generation and detection



1 or 2 stop bit generation



Support of software flow control using programmable Xon/Xoff characters



False start bit detection



Line break generation and detection



Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO



Programmable FIFO disabling for 1-byte depth data path

These UARTs vary from industry-standard 16C650 on some minor points which are:



Receive FIFO trigger levels



The internal register map address space, and the bit function of each register differ



The deltas of the modem status signals are not available



1.5 stop bits is not supported



Independent receive clock feature is not supported

3.4.3

I2C

STA8090GA includes an I2C interface configurable as master or slave.

3.4.4

MTU

The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit

Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,

allowing the counters to run from a much slower clock than the system clock.

The FRC is the part of the timer that performs the counting. There are four instantiations of

the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit

counter in the FRC is split up into two 16-bit counters.

3.4.5

WDT

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog

clock is used to generate a regular interrupt (WDOGINT), depending on a programmed

value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt

remains unserviced for the entire programmed period. You can enable or disable the

watchdog unit as required.

Note:

Watchdog is stalled when the ARM processor is in Debug mode.

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