6.1

Guidelines

1.

Input signals HIN, LIN are active-high logic. A 100 kΩ (typ.) pull-down resistor is built-in for each input pin.

To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of

RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100

ns and placed as close as possible to the IPM input pins.

2.

The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the

power supply. Besides, to reduce any high-frequency switching noise distributed on the power lines, a

decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible

to each Vcc pin and in parallel with the bypass capacitor.

3.

The use of an RC filter (RSF, CSF) prevents protection circuit malfunctions. The time constant (RSF x CSF)

should be set to 1 µs and the filter must be placed as close as possible to the CIN pin.

4.

The SD is an input/output pin (open-drain type if it is used as output). It should be pulled up to a power

supply (i.e., MCU bias at 3.3/5 V) by a resistor value, which can keep the Iod no higher than 5 mA (VOD ≤

500 mV when open-drain MOSFET is ON). The filter on SD should be sized to get a desired re-starting time

after a fault event and placed as close as possible to the SD pin.

5.

A decoupling capacitor CTSO (between 1 nF and 10 nF) placed close to the MCU can be used to increase

the noise immunity of the TSO thermal sensor.

6.

The decoupling capacitor C3 (100 to 220 nF with low ESR and low ESL) in parallel with each Cboot filters

high-frequency disturbances. Both Cboot and C3 (if present) should be placed as close as possible to the

U,V,W and Vboot pins. Bootstrap negative electrodes should be connected to the U,V,W terminals directly

and separated from the main output wires.

7.

To prevent overvoltage on the VCC pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener

diode (Dz2) can be placed in parallel with each Cboot.

8.

The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the

electrolytic capacitor CVdc prevents surge destruction. Both capacitors C4 and CVdc should be placed as

close as possible to the IPM (C4 has priority over Cvdc).

9.

By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals

without an optocoupler is possible.

10. Low inductance shunt resistors should be used for phase leg current sensing.

11. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as

possible.

12. The connection of the SGN_GND to the PWR_GND at one point only (close to the shunt resistor terminal)

can reduce the impact of power ground fluctuation.

These guidelines ensure the device specifications for application designs. For further details, please refer to the

relevant application note.

Table 12. Recommended operating conditions

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VPN

Supply voltage

Applied among P-Nu, NV, Nw

300

400

V

VCC

Control supply voltage

Applied to VCC-GND

13.5

15

18

V

VBS

High-side bias voltage

Applied to VBOOTi-OUTi for i = U, V, W

13

18

V

tdead

Blanking time to prevent arm-short For each input signal

1.5

µs

fPWM

PWM input signal

-40 °C < TC < 100 °C

-40 °C < TJ < 125 °C

20

kHz

TC

Case operation temperature

100

°C

STIB1560DM2-L

Guidelines

DS13085 - Rev 1

page 16/22