LM27213 datasheet(15/22 Pages) NSC

15 / 22 page

Applications Information (Continued)

simply 20µA divided by the desired slew rate. For an output

voltage rate of rise of 1V/ms, the capacitor should be about

20nF.

SOFT STOP

When VRON is deasserted, the LM27213 starts to discharge

the soft start capacitor with an internal 45µA current sink.

core is forced to follow the resulting linear ramp voltage on

the soft start capacitor downward. When V

core reaches ap-

proximately 300mV the high-side FET is disabled and the

low-side FET is turned on to quickly discharge the output to

zero and hold it there. This forces a controlled turn off slew

rate that eliminates the possibility of the output voltage ring-

ing significantly below ground. It can also be helpful in the

sequencing of multiple supply rails.

STARTUP SEQUENCING

At initial power up the LM27213 targets a voltage equal to

boot. This is the voltage level set at the VBOOT pin (27) by

a resistor divider that is powered by the V1R7 reference

output (pin 26). This divider also has taps for the OVP

threshold and deeper sleep voltage set point. The regulator’s

output will remain at V

boot until a time Tboot after the XPOK

flag clears. T

boot is nominally 20µs. After the Tboot time

expires CLK_EN# will be asserted and the output will tran-

sition to the voltage selected by the VID bits. Power good will

be enabled nominally 5ms after CLK_EN# is asserted.

DYNAMIC VID TRANSITIONS

Upon detecting a VID or mode change the LM27213 masks

the power good comparator for a period of approximately

130µs. During the blanking interval the power good output is

forced high while the output voltage is in slew to the newly

selected level. The slew rate is determined by the soft start

capacitor value. The charge/discharge current driving the

soft start capacitor will be 350µA typically. The programmed

slew rate is therefore 350µA divided by the soft start pin

capacitance.

STOP CPU MODE

If the STP_CPU# pin (34) is asserted with SLP de-asserted

the VREF pin voltage will be forced to the voltage on the

VSTP pin (32). The output will slew at a rate determined as

above to the new value. The PGOOD mask is in effect for

130µs.

SLEEP MODE

To enable sleep mode both STP_CPU# and SLP need to be

asserted. The VREF pin voltage will transition to the voltage

on the VSLP pin with a slew rate as discussed under ynamic

VID transitions and the PGOOD mask is activated for 130µs.

POWER SAVING MODE

The LM27213 allows for high efficiency operation at very low

power levels by employing a diode emulator mode. This can

be activated in either deep sleep or deeper sleep modes

only. Assert the DE_EN# pin while in a sleep mode to

activate this function. When operating at low power the

LM27213 detects inductor current reversal with a zero cross

detector connected to the drain of the low-side FET. The

voltage at this node is normally below ground when the low

side FET is on but will become positive when the inductor

current reverses. When the inductor current reversal is de-

tected the low side switch is turned off and essentially be-

comes a nearly ideal diode. Due to the hysteretic control

mode, the regulator operating frequency will be greatly re-

duced at light loads. High-side switch on-time will not change

significantly compared to normal operation, but the off times

will extend greatly. Care must be taken to connect the SRCK

(Source Kelvin, pin 5) close to the low-side switch source

connection, as this is the reference input to the zero cross

detector.

Component Selection

There are numerous tradeoffs to be made in settling on a

final set of component choices and as a result the process

tends to be somewhat iterative. There’s always more than

one combination of parts that will work in a given application.

We will start with a few rule of thumb assumptions and then

adjust as required to find a combination that meets the

specification requirements and is cost effective. Some of the

choices can be thought of as somewhat philosophical.

Let’s start the design by choosing an inductor and then

develop the remainder of the design around that choice.

INDUCTOR SELECTION

A good place to start is by choosing an appropriate buck

inductor. A decent rule of thumb is to allow the worst case,

peak to peak ripple current to be on the order of 40% to 50%

of the full load output current. So, for a design of 12A at full

load, the ripple current should be in the range of 4.8A to 6A.

Larger or smaller ripple currents may well be acceptable but

there are tradeoffs associated with these choices. As induc-

tor value increases, there is a corresponding need to in-

crease the amount of output capacitance to handle load

transients. Conversely, as inductance is reduced, the RMS

switch currents tend to rise and therefore efficiency suffers

slightly while dynamic performance is improved.

The worst case ripple current will occur at the combination of

maximum input and output voltage. Let’s assume an output

voltage of 1.180V and a maximum input of 16V. This will

assume operation on a wall adapter while battery voltage

may be only 12V maximum. Another assumption that must

be made is the intended operating frequency. Again there

exists a tradeoff between dynamic performance and effi-

ciency. The “sweet spot” at the time of this writing is roughly

in the range of 300kHz to 400kHz. That will in all likelihood

shift positive in time as FET technology improves. The hys-

teretic architecture also varies the operating frequency as a

function of input voltage with the regulator tending to run a bit

slower at high input voltages. Let’s assume a 300kHz fre-

quency at high input line. Also, since the efficiency is of

somewhat less of a concern when operating from a wall

adapter we’ll design for the high end of the ripple current

range under this condition. The ripple current will be lower

when operating from a battery since the input voltage will be

lower and the switching frequency will be somewhat higher.

With all that settled let’s calculate a value for L.

L= (V

IN-VO)VO/(

∆IxV

IN xfSW)

Where:

L is the inductor value

in is the input voltage

o is the output voltage

∆I is the ripple current

sw is the switching frequency

So,

L = (16V-1.18V)1.18V/(6A x 16V x 300kHz)

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