VSC8540RT datasheet(32/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 32

 2022 Microchip Technology Inc. and its subsidiaries

5.12

Wake-On-LAN and SecureOn

The VSC8540RT device supports Wake-on-LAN, an Ethernet networking standard to awaken hosts by using a “magic

packet” that is decoded to ascertain the source, and then assert an interrupt pin or a LED. The VSC8540RT device also

supports SecureOn to secure Wake-on-LAN against unauthorized access. The following illustration shows an overview

of the Wake-on-LAN functionality.

FIGURE 5-15:

WAKE-ON-LAN FUNCTIONALITY

Wake-on-LAN detection is available in 10BASE-T and 100BASE-TX modes. It is enabled by setting the interrupt mask

using register 27E2. The MAC address is saved in its local register space (21E2, 22E2, and 23E2).

5.13

Fast Link Failure Indication

For 10BASE-T links, the fast link failure indication matches the link status register (address 1, bit 2). For 100BASE-TX

links, the link failure is based on a circuit that analyzes the integrity of the link and will assert at the indication of failure

(< 3 ms. worst case).

FLF indication works for all copper media speeds through the FASTLINK_FAIL pin. Fast link failure is supported through

the MDINT (active low) pin only in 100BASE-TX mode. It is not supported through the MDINT pin and interrupt status

Note:

A system can later confirm the fast link down indication for system management purposes by actively polling

the link status bit to determine if a link has failed.

Note:

Fast Link Failure Indication and Fast Link Failure 2 Indication should not be used when EEE is enabled on

a link.

5.14

Fast Link Failure 2™ (FLF2™) Indication

In order to enable specific industrial applications in which the system must be warned as quickly as possible that a link

might be going down, the VSC8540RT device features the FLF2 indicator function. This new feature enables the PHY

to indicate the onset of a potential link failure in less than 150 µs for 100BASE-TX operation. FLF2 is supported through

the FASTLINK_FAIL pin.

This new functionality goes beyond the normal FLF indicator function, which must be enabled concurrently with FLF2,

and is enabled by writing a 1 to bit 15 of register 20E2.

A system can later confirm the fast link down indication for system management purposes by actively polling the link

status bit to determine if a link has failed.

Note:

For 10/100 links, the notification timing performance is only guaranteed for link loss due to failure of the PHY

MDI pair operating as the ingress (receive) pair to the PHY.

Note:

FLF2 should not be used when EEE is enabled on a link.

Tx Path

Rx Path

Wake-on-LAN

Detect

WOL_MAC_ADDR

ADDR_REPEAT_CNT

Secure-On enable

Secure-On

password length

Secure-On password

WoL Detected

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