Data Sheet

ADE9430

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

27

VDD

Supply Voltage. The VDD pin provides the supply voltage. Decouple VDD to GND with a ceramic 0.1 µF capacitor in parallel with a

10 µF ceramic capacitor.

28

GND

Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

29

CLKIN

Crystal/Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. Alternatively, an external clock can be

provided at this logic input.

30

CLKOUT

Crystal Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. When using CLKOUT to drive external

circuits, connect an external buffer.

31

IRQ0

Interrupt Request Output. This pin is an active low logic output. See the Interrupts and Events section for information about events

that trigger interrupts.

32

IRQ1

Interrupt Request Output. This pin is an active low logic output. See the Interrupts and Events section for information about events

that trigger interrupts.

33

CF1

Calibration Frequency Logic Output 1. The CF1, CF2, CF3, and CF4 outputs provide power information based on the CFxSEL bits

in the CFMODE register. Use these outputs for operational and calibration purposes. Scale the full-scale output frequency by writing

to the CFxDEN registers (see the Digital to Frequency Conversion—CFx Output section and the ADE9430 Technical Reference

Manual).

34

CF2

CF Logic Output 2. This pin indicates CF2.

35

CF3/ZX

CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing.

36

CF4/EVENT/DREADY

CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready.

37

SCLK

Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing On-Chip Data section).

The SCLK pin has a Schmitt trigger input for use with a clock source that has a slow edge transition time, for example, optoisolator

outputs.

38

MISO

Data Output for the SPI Port.

39

MOSI

Data Input for the SPI Port.

40

SS

Chip Select for the SPI Port.

EPAD

Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the PCB to confer

mechanical strength to the package and connect all grounds (GND, AGND, DGND, and REFGND) together at this point.