MDT2030(CC)

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P. 2

2005/6

Ver. 1.4

5. Block Diagram

S ta ck Tw o Le ve ls

P ro g ra m C o u n te rs

O s cilla to r Circu it

P o we r o n Re s e t

P o w e r Do wn R e s e t

8 -b it Tim e r/Co u n te r

E P R O M

2 0 4 8 X1 4

In s tru ctio n

Re g is te r

In s tru ctio n

De co d e r

W o rkin g R e g is te r

ALU

P re s ca le

RAM

7 3 X8

S p e c ia l Re g is te r

Co n tro l C ircu it

S ta tu s R e g is te r

W DT/O S T

Tim e r

P o rt A

P o rt B

O S C 1

O S C 2

MCLR

Da ta

8 -b it

R TCC

1 1 b its

1 1 b its

1 4

b its

P o rt

P A0 ~P A3

4 b its

P o rt

P B0 ~ P B7

8 b its

D 0 ~D 7