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MAX1672C/D Fiches technique(PDF) 5 Page - Maxim Integrated Products |
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MAX1672C/D Fiches technique(HTML) 5 Page - Maxim Integrated Products |
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5 / 11 page ![]() Step-Up/Down DC-DC Converter in QSOP Package _______________________________________________________________________________________ 5 ______________________________________________________________Pin Description NAME FUNCTION 1 LX Inductor Connection to the Drain of the Internal N-Channel Power MOSFET PIN Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) A B 10 µs/div OUTPUT RIPPLE (HEAVY LOAD) MAX1672-13 A: VOUT = 5V (20mV/div, AC COUPLED) B: IL1 (500mA/div) (VIN = 2.7V, IOUT = 250mA) A B 50 µs/div STARTUP DELAY MAX1672-14 A: VOUT = (2V/div) B: ONB (2V/div) (VIN = 2.7V, RLOAD = 50Ω) A B 200 µs/div TURN-OFF DELAY MAX1672-15 A: VOUT = (2V/div) B: ONB (2V/div) (VIN = 2.7V, RLOAD = 50Ω) 2 PGND Power Ground 3 ONB On Control Input. When ONB = low or ONA = high, the IC is on. Connect ONB to GND for normal operation (Table 1). 4 ONA On Control Input. When ONA = low and ONB = high, the IC is off. Connect ONA to PS for normal operation (Table 1). 5 3/5 Output Voltage Selection Input. Connect to PS for 3.3V output and to GND for 5V output. With VFB > 80mV, the state of the 3/5 pin is ignored (Table 2). 6 PGI Low-Battery Detector Input (1.25V threshold) 7 PGO Low-Battery Detector Output (open drain). PGO pulls low when VPGI is greater than 1.25V. 8 ILIM Inductor-Current-Limit Selection Input. Connect to PS for 0.8A current limit and to GND for 0.5A current limit. 9 OUT Regulator Output. Drain of internal PFET linear regulator. Bypass with a 4.7µF capacitor to GND. 10 FB Feedback Input. For 3.3V or 5V output, connect to GND. For adjustable output, connect to feedback resistor- divider network. With VFB > 70mV, the state of the 3/5 pin is ignored. 11 PS Bootstrapped Power Supply. Output of step-up switch-mode regulator and source of internal PFET linear regulator. The IC is powered from this pin. 12 IN Input Voltage Sense Input. Connect to input supply. 13 REF Reference Voltage Output. Bypass with a 0.1µF capacitor to GND. 14 GND Analog Ground 15 PGND Power Ground 16 LX Inductor Connection to the Drain of the Internal N-Channel Power MOSFET |
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