ADP5034AREZ-1-R7 datasheet(25/28 Pages) AD

No de pièce	ADP5034AREZ-1-R7

Description	Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs

PDF	28 Pages

Scroll/Zoom	100%

Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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25 / 28 page

Data Sheet

ADP5034

Rev. E | Page 25 of 28

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5034 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines. Also, refer to the

UG-271 and UG-439 user guide.

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the

component side ground to further reduce noise

interference on sensitive circuit nodes.

•

Connect VIN1, VIN2, and AVIN together close to the IC

using short tracks.

ADP5034AREZ-1-R7 Fiches technique(PDF) 25 Page - Analog Devices