STM32WB50CG datasheet(52/119 Pages) STMICROELECTRONICS

No de pièce	STM32WB50CG

Description	Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 or 802.15.4 radio solution

PDF	119 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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52 / 119 page

Memory mapping

STM32WB50CG STM32WB30CE

52/119

DS13047 Rev 5

Memory mapping

The STM32WB50CG and STM32WB30CE devices feature a single physical address space

that can be accessed by the application processor and by the RF subsystem.

A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,

exclusively accessible by the CPU2, protected against execution, read and write from CPU1

and DMA.

In case of shared resources the SW should implement arbitration mechanism to avoid

access conflicts. This happens for peripherals Reset and clock controller (RCC), Power

controller (PWC), EXTI and Flash interface, and can be implemented using the built-in

semaphore block (HSEM).

By default the RF subsystem and CPU2 operate in secure mode. This implies that part of

the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by

the CPU2. In this case the Host processor (CPU1) has no access to these resources.

The detailed memory map and the peripheral mapping of the devices can be found in the

reference manual RM0471.

STM32WB50CG Fiches technique(PDF) 52 Page - STMicroelectronics