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SPC58EEX Fiches technique(PDF) 107 Page - STMicroelectronics |
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SPC58EEX Fiches technique(HTML) 107 Page - STMicroelectronics |
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107 / 154 page ![]() DS11646 Rev 4 107/154 SPC58EEx, SPC58NEx Electrical characteristics 128 Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0 Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Data Last Data First Data First Data Data Last Data SIN SOUT PCSx SCK Output SCK Output (CPOL = 0) (CPOL = 1) tSCK tSDC tSDC tCSC tASC tSUI tHI tSUO tHO Data Last Data First Data SIN SOUT Last Data Data First Data SCK Output SCK Output PCSx (CPOL = 0) (CPOL = 1) tSUI tHI tSUO tHO tHI |
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