ST25R3911B datasheet(71/116 Pages) STMICROELECTRONICS

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1.3.21

Mask main interrupt register

Address: 14h

Type: RW

Table 47. Mask main interrupt register

Bit

Name

Default

Function

Comments(1)

M_osc

1: Mask IRQ when oscillator frequency is stable

M_wl

1: Mask IRQ due to FIFO water level

M_rxs

1: Mask IRQ due to start of receive

M_rxe

1: Mask IRQ due to end of receive

M_txe

1: Mask IRQ due to end of transmission

M_col

1: Mask IRQ due to bit collision

Not used

1. Default setting takes place at power-up and after set default command.

1.3.22

Mask timer and NFC interrupt register

Address: 15h

Type: RW

Table 48. Mask timer and NFC interrupt register

Bit

Name

Default

Function

Comments(1)

M_dct

1: Mask IRQ due to termination of direct command

M_nre

1: Mask IRQ due to No-Response Timer expire

M_gpe

1: Mask IRQ due to general purpose timer expire

M_eon

1: Mask IRQ due to detection of external field higher than Target activation level

M_eof

1: Mask IRQ due to detection of external field drop below Target activation level

M_cac

1: Mask IRQ due to detection of collision during RF Collision Avoidance

M_cat

1: Mask IRQ after minimum guard time expire

M_nfct

1: Mask IRQ when in target mode the initiator bit rate was recognized

1. Default setting takes place at power-up and after set default command.

ST25R3911B

Registers

DS11793 - Rev 6

page 71/116

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