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PCF85363ATL/A Fiches technique(PDF) 68 Page - NXP Semiconductors

No de pièce PCF85363ATL/A
Description  Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus
PDF  86 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF85363ATL/A Fiches technique(HTML) 68 Page - NXP Semiconductors

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NXP Semiconductors
PCF85363A
Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,
and I2C-bus
aaa-010607
0
1
2
3
4
5
6
-0.4
-0.2
0
0.2
0.4
VDD (V)
Δfosc/fosc
Δfosc/fosc
(ppm)
(ppm)
(1)
(1)
(2)
(2)
(3)
(3)
Tamb = 25 °C.
1. CL(itg) = 12.5 pF.
2. CL(itg) = 6 pF.
3. CL(itg) = 7 pF.
Figure 40. Oscillator frequency variation with respect to VDD
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and
VIH with an input voltage swing of VSS to VDD [1] .
Symbol
Parameter
Conditions
Min
Max
Unit
Cb
capacitive load for
each bus line
-
400
pF
fSCL
SCL clock frequency
[2] 0
400
kHz
tHD;STA
hold time (repeated)
START condition
0.6
-
μs
tSU;STA
set-up time for a
repeated START
condition
0.6
-
μs
tLOW
LOW period of the
SCL clock
1.3
-
μs
tHIGH
HIGH period of the
SCL clock
0.6
-
μs
tr
rise time of both SDA
and SCL signals
20
300
ns
tf
fall time of both SDA
and SCL signals
[3] [4] 20 × (VDD / 5.5 V) 300
ns
tBUF
bus free time between
a STOP and START
condition
1.3
-
μs
tSU;DAT
data set-up time
100
-
ns
Table 68. I2C-bus characteristics
PCF85363A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3.1 — 18 June 2021
68 / 86



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