MMPF0200Z datasheet(69/118 Pages) NXP

69 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well

as programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for

this. Table 78 presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior

of the LDO output.

Table 77. VGEN3/ 4/ 5/ 6 Output Voltage Configuration

Set Point

VGENx[3:0]

VGENx Output (V)

0000

1.80

0001

1.90

0010

2.00

0011

2.10

0100

2.20

0101

2.30

0110

2.40

0111

2.50

1000

2.60

1001

2.70

1010

2.80

1011

2.90

1100

3.00

1101

3.10

1110

3.20

1111

3.30

Table 78. LDO Control

VGENxEN

VGENxLPWR

VGENxSTBY

STANDBY(50)

VGENxOUT

Off

Low Power

Off

Low Power

Notes

50.

STANDBY refers to a Standby event as described earlier.

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