ML7005MB datasheet(5/25 Pages) OKI

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ML7005

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Symbol

Type

Description

READ

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the read control input pin. When this pin is set to "0", data in the

specified register is output to the bus lines (D3 to D0). At that time, CS must be "0".

See the figure 4 for processor interface timing.

When PTYPE is "0" (Motorola processor mode) :

This pin is the clock input pin (equivalent to SCLK of the MSM7524).

When in Write mode, data in D3 to D0 is written to the specified register at the

falling edge of the READ signal.

When in Read mode, data in the specified register is output to D3 to D0 when the

READ signal is "1", and D3 to D0 is opened when the READ signal is "0".

The READ signal is not necessarily a periodical signal.

See the figure 5 for processor interface timing.

Chip select input pin for processor interface.

When the CS signal is "0", read and write operations are possible.

When the CS signal is "1", read and write operations are impossible.

ALE

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the address latch enable input pin.

The register address data in D1 to D0 is latched at the falling edge of ALE.

When PTYPE is "0" (Motorola processor mode) :

This pin is the address data input pin (equivalent to AD0 of the MSM7524).

When this pin is "1", data can be written to the control register (CR) and data can

be read from the status register (STR).

When this pin is "0", data can be written to the DTMF transmit register (DTMFT)

and data can be read from the DTMF receive register (DTMFR).

Input pin for processor interface.

When PTYPE is "1" (Intel processor mode) :

This pin is the Write control input.

Data in the data bus lines (D3 to D0) is written to the specified register. At that time,

CS must be "0".

When PTYPE is "0" (Motorola processor mode) :

This is the signal input pin for controlling the Read and Write modes

(equivalent to R/W of the MSM7524).

When this pin is "1", the LSI enters the Read mode. When this pin is "0", the LSI

enters the Write mode.

18 - 21

I/O

D3 - D0

4-bit data bus I/O pins for processor interface.

When PTYPE is "1" (Intel processor mode), D1 and D0 are also used for addressing.

CPDO

Digital output pin for CPT detector.

When a 400 Hz signal is input to the CPDIP and CPDIM pins, this pin is "1".

When the DOEN register is "0", this pin is fixed at "0".

—

GND

Ground pin.

DTGO

Analog output pin for DTMF signal generator.

The tone amplitude is approximately - 9.0 dBm for a low group and approximately

- 7.0 dBm for a high group. The transmit signal level can be changed by using the

DTAI and DTAO pins. See the figure 11 for adjusting the transmit signal level.

Control the ON/OFF of signal transmission by using MFC of the control register.

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