ICS671M-06ILFT datasheet(4/6 Pages) ICST

4 / 6 page

3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

MDS 671-06 D

Revision 050405

Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l

www.icst.com

ICS671-06

AC Electrical Characteristics

VDD = 3.3 V ±5%

, Ambient Temperature -40 to +85°C, CLOAD at CLK = 15 pF, unless stated otherwise

Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz.

Note 2: When there is no clock signal present at CLKIN, the ICS671-06 will enter power down mode. The

PLL is stopped and the outputs are tri-state.

Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN.

Output High Voltage

VOH

IOH = -12 mA

2.4

Output Low Voltage

VOL

IOL = 12 mA

0.4

Output High Voltage,

CMOS level

VOH

IOH = -12 mA

VDD-0.4

Operating Supply Current

IDD

No Load, S2 = 1, S1 = 1,

Note 1

Power Down Supply

Current

IDD

CLKIN = 0, S2 = 0, S1 = 1

µA

CLKIN = 0, Note 2

µA

Short Circuit Current

IOS

Each output

±50

Input Capacitance

CIN

S2, S1, FBIN

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Input Clock Frequency

fIN

See table on page 2

133

MHz

Output Clock Frequency

See table on page 2

133

MHz

Output Rise Time

tOR

0.8 to 2.0 V, CL = 30 pF

2.5

Output Fall Time

tOF

2.0 to 0.8 V, CL = 30 pF

2.5

Output Clock Duty Cycle

tDC

Measured at VDD/2

Device to Device Skew

Rising edges at VDD/2

700

Output to Output Skew

Rising edges at VDD/2

200

Input to Output Skew

Rising edges at VDD/2, FBIN to

CLKA4, S1 = 1, S0 = 1, Note 1

±250

Maximum Absolute JItter

130

200

Cycle to Cycle Jitter

30 pF, measured at 66.67M

200

15 pF, measured at 66.67M

200

15 pF, measured at 133.33M

100

PLL Lock Time

Note 3

1.0

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