ICS671-03

3.3 Volt Zero Delay, Low Skew Buffer

MDS 671-03 A

2

Revision 072501

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com

PRELIMINARY INFORMATION

Pin Descriptions

Key: I = Input; O = output; P = power supply connection. Outputs have a weak internal pull-down when in tri-state

mode.

Pin Assignment

External Components

The ICS671-03 requires a minimum number of external components for proper operation. Decoupling capacitors of

0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as

close to the device as possible. A series termination resistor of 33

Ω may be used close to each clock output pin to

reduce reflections.

16

15

14

13

16 pin narrow (150 mil) SOIC

12

11

10

9

1

2

3

4

5

6

7

8

CLKA1

GND

FBIN

CLKIN

VDD

S2

CLKB1

CLKB2

VDD

GND

CLKB3

S1

CLKB4

CLKA4

CLKA3

CLKA2

Number

Name

Type

Description

1

CLKIN

I

Clock Input. (5 V tolerant)

2, 3, 14, 15

CLKA1:A4

O

Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.

4, 13

VDD

P

Power supply. Connect both pins to 3.3 V.

5, 12

GND

P

Connect to ground.

6, 7, 10, 11

CLKB1:B4

O

Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.

8

S2

I

Select input 2. See table above. Internal pull-up.

9

S1

I

Select input 1. See table above. Internal pull-up.

16

FBIN

I

Feedback Input. Connect to any output under normal operation. (5 V tolerant)

S2

S1

CLKA1:A4

CLKB1:B4

A & B Source

PLL Status

0

0

Tri-state (Note 1)

Tri-state (Note 1)

PLL

ON

0

1

Stopped Low

Stopped Low

none

OFF

1

0

Running

Running

CLKIN (Note 2)

OFF

1

1

Running

Running

PLL

ON

Output Clock Mode Select Table

Notes: 1. Outputs are in high impedance state with weak pulldowns.

2. Buffer mode only; not zero delay between input and output.