ICS5310AI01L datasheet(5/15 Pages) ICST

5 / 15 page

85310AYI-01

www.icst.com/products/hiperclocks.html

REV. F JANUARY16, 2006

Integrated

Circuit

Systems, Inc.

ICS85310I-01

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER

ADDITIVE PHASE JITTER

Additive Phase Jitter, RMS

@ 155.52MHz = <0.13ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100

10k

100k

10M

100M

The spectral purity in a band at a specific offset from the funda-

mental compared to the power of the fundamental is called the

dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise

power present in a 1Hz band at a specified offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in

As with most timing specifications, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise floor of the equipment is higher than

the noise floor of the device. This is illustrated above. The de-

the 1Hz band to the power in the fundamental. When the re-

quired offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the funda-

mental. By investigating jitter in the frequency domain, we get a

better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

vice meets the noise floor of what is shown, but can actually be

lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

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