| Moteur de recherche de fiches techniques de composants électroniques |
|
ICS83841BHT Fiches technique(PDF) 4 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS83841BHT Fiches technique(HTML) 4 Page - Integrated Circuit Systems |
|
4 / 8 page ![]() 83841BH www.icst.com/products/hiperclocks.html REV. A JANUARY 20, 2006 4 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX t PD V DD 2 V DD 2 PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 2.5V OUTPUT LOAD AC TEST CIRCUIT BANK SKEW tsk(o) V DD 2 V DD 2 DAx, DBx DAy, DBy DHx DAx/DBx 1.25V 1.25V 1.25V 2.5V 0V VOH VOL Input Output Rising Edge Skew FallingEdge Skew 1.25V 1.25V 1.25V 1.25V VOH - 0.15V VOL VOH 0V 2.5V tPHZ → tPZH → Output DAx/DBx (See Note) S (Low-level enabling) NOTE: The output is high except when disabled by the S control. ← 3-STATE OUTPUT ENABLE/DISABLE TIMES RISING & FALLING EDGE SKEW PROPAGATION DELAY tsk(b) V DD 2 V DD 2 DAx DBx V DD = 1.25V ± 0.1V -1.25V ± 0.1V SCOPE Qx LVCMOS V DD GND This circuit is used for test purposes only, not intended for application use. |
|
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |