AT45DB321E datasheet(8/70 Pages) DIALOG

8 / 70 page

AT45DB321E

8784L–DFLASH–3/2019

the device will continue reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum

SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array

Read bypasses the data buffers and leaves the contents of the buffers unchanged.

Warning:

This command is not recommended for new designs.

5.2

Continuous Array Read (High Frequency Mode: 1Bh Opcode)

This command can be used to read the main memory array sequentially at the highest possible operating clock

frequency up to the maximum specified by f

CAR4. To perform a Continuous Array Read using the standard DataFlash

page size (528 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device

followed by three address bytes and two dummy bytes. The first 13 bits (PA12 - PA0) of the 23-bit address sequence

specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequence

specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (512

bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A21 - A0) and two dummy

bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO

(Serial Output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of

data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue

reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover

from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum

SCK frequency allowable for the Continuous Array Read is defined by the f

CAR1 specification. The Continuous Array

Read bypasses both data buffers and leaves the contents of the buffers unchanged.

5.3

Continuous Array Read (High Frequency Mode: 0Bh Opcode)

This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum

specified by f

CAR1. To perform a Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin

must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and

one dummy byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory

array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the

page. To perform a Continuous Array Read using the binary page size (512 bytes), the opcode 0Bh must be clocked into

the device followed by three address bytes (A21 - A0) and one dummy byte. Following the dummy byte, additional clock

pulses on the SCK pin will result in data being output on the SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of

data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue

reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover

from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum

SCK frequency allowable for the Continuous Array Read is defined by the f

CAR1 specification. The Continuous Array

Read bypasses both data buffers and leaves the contents of the buffers unchanged.

5.4

Continuous Array Read (Low Frequency Mode: 03h Opcode)

This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum

specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for the lower

AT45DB321E Fiches technique(PDF) 8 Page - Dialog Semiconductor

AT45DB321E Fiches technique(HTML) 8 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Fiches technique Télécharger

Lien URL