ADPA7005CHIP datasheet(20/23 Pages) AD

20 / 23 page

ADPA7005CHIP

Data Sheet

Rev. 0 | Page 20 of 23

Figure 59. IDD vs. RF Input Power (PIN), VDD = 5 V, Frequency = 32 GHz for

Constant Drain Current Bias and Constant Gate Voltage Bias

Figure 60. POUT vs. PIN, VDD = 5 V, Frequency = 32 GHz, Constant Drain

Current Bias and Constant Gate Voltage Bias

Figure 61. PAE vs. PIN, VDD = 5 V, Frequency = 32 GHz, Constant Drain

Current Bias and Constant Gate Voltage Bias

Figure 62. Output P1dB vs. PIN, VDD = 5 V, Frequency = 32 GHz, Constant

Drain Current Bias and Constant Gate Voltage Bias

2000

1000

1200

1500

1600

1800

1900

1400

1100

1300

1700

–6

–4

–2

PIN (dBm)

CONSTANT GATE VOLTAGE BIAS

CONSTANT DRAIN CURRENT BIAS

–6

–4

–2

PIN (dBm)

CONSTANT GATE VOLTAGE BIAS

CONSTANT DRAIN CURRENT BIAS

–6

–4

–2

PIN (dBm)

CONSTANT GATE VOLTAGE BIAS

CONSTANT DRAIN CURRENT BIAS

PIN (dBm)

CONSTANT GATE VOLTAGE BIAS

CONSTANT DRAIN CURRENT BIAS

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