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PL611-07XXXTC-R Fiches technique(PDF) 2 Page - PhaseLink Corporation

No de pièce PL611-07XXXTC-R
Description  Programmable Quick Turn Clock
PDF  4 Pages
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Fabricant  PLL [PhaseLink Corporation]
Site Internet  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL611-07XXXTC-R Fiches technique(HTML) 2 Page - PhaseLink Corporation

  PL611-07XXXTC-R Datasheet HTML 1Page - PhaseLink Corporation PL611-07XXXTC-R Datasheet HTML 2Page - PhaseLink Corporation PL611-07XXXTC-R Datasheet HTML 3Page - PhaseLink Corporation PL611-07XXXTC-R Datasheet HTML 4Page - PhaseLink Corporation  
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PL611-07
Programmable Quick Turn ClockTM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/17/05 Page 2
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
VDD
+0.5
V
Output Voltage Range
VO
-0.5
VDD
+0.5
V
Soldering Temperature (Green package)
260
°C
Data Retention @ 85
°C
10
Year
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature
-40
85
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Input Frequency(XIN)
Fundamental Crystal
10
30
MHz
Input (FIN) Frequency
100
MHz
Input (FIN) Signal Amplitude
Internally AC coupled
0.9
VDD
Vpp
Settling Time
At power-up (after VDD increases over 1.62V)
10
ms
15pF Load, 10/90%VDD, Standard drive
2.5
3.5
ns
Output Rise Time
15pF Load, 10/90%VDD, High drive
1.0
1.5
ns
15pF Load, 90/10%VDD, Standard drive
2.5
3.5
ns
Output Fall Time
15pF Load, 90/10%VDD, High drive
1.0
1.5
ns
Duty Cycle
At VDD/2
45
50
55
%
Period Jitter, peak-to-peak*
(measured from 10,000 samples)
With capacitive decoupling between VDD and
GND. Operating only one output.
70
ps
* Note: Jitter performance depends on the programming parameters.



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