M40Z300AV datasheet(4/20 Pages) STMICROELECTRONICS

4 / 20 page

M40Z300AV

4/20

DESCRIPTION

The M40Z300AV NVRAM SUPERVISOR is a self-

contained device which converts a standard low-

power SRAM into a non-volatile memory. A preci-

sion voltage reference and comparator monitors

the VCC input for an out-of-tolerance condition.

When an invalid VCC condition occurs, the condi-

tioned chip enable outputs (E1CON to E4CON) are

forced inactive to write-protect the stored data in

the SRAM. During a power failure, the SRAM is

switched from the VCC pin to the lithium cell within

the SNAPHAT® to provide the energy required for

data retention. On a subsequent power-up, the

SRAM remains write protected until a valid power

condition returns.

The 28-pin, 330mil SOIC provides sockets with

gold plated contacts for direct connection to a sep-

arate SNAPHAT housing containing the battery.

The SNAPHAT housing has gold plated pins

which mate with the sockets, ensuring reliable

connection. The housing is keyed to prevent im-

proper insertion. This unique design allows the

SNAPHAT battery package to be mounted on top

of the SOIC package after the completion of the

surface mount process which greatly reduces the

board manufacturing process complexity of either

directly soldering or inserting a battery into a sol-

dered holder. Providing non-volatility becomes a

“SNAP.” The 16-pin SOIC provides battery pins for

an external user-supplied battery.

Insertion of the SNAPHAT housing after reflow

prevents potential battery damage due to the high

temperatures required for device surface-mount-

ing. The SNAPHAT housing is also keyed to pre-

vent reverse insertion.

The 28-pin SOIC and battery packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. For the 28-lead SOIC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber

“M4ZXX-BR00SH”

(see

Table

13., page 18).

Caution: Do not place the SNAPHAT battery top

in conductive foam, as this will drain the lithium

button-cell battery.

Figure 3. Logic Diagram

Note: 1. For 16-pin SOIC package only.

2. THS pin must be connected to VSS.

Table 1. Signal Names

Note: 1. THS pin must be connected to VSS.

2. For M40Z300AV, B– must be connected to the negative

battery terminal only (not to Pin 8, VSS).

AI08893

THS

(2)

VCC

M40Z300AV

VSS

VOUT

E1CON

E2CON

E3CON

E4CON

RST

B+

(1)

B–

(1)

THS(1)

Threshold Select Input

Chip Enable Input

E1CON - E4CON

Conditioned Chip Enable

Output

A, B

Decoder Inputs

RST

Reset Output (Open Drain)

Battery Low Output (Open

Drain)

VOUT

Supply Voltage Output

VCC

Supply Voltage

VSS

Ground

B +

Positive Battery Pin

B –(2)

Negative Battery Pin

Not Connected Internally

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