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STM32H723VG Fiches technique(PDF) 151 Page - STMicroelectronics

No de pièce STM32H723VG
Description  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
PDF  227 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H723VG Fiches technique(HTML) 151 Page - STMicroelectronics

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DS13313 Rev 2
151/227
STM32H723xE/G
Electrical characteristics
208
Figure 32. OCTOSPI SDR read/write timing diagram
tw(CKH)
OCTOSPI clock high and low
time, even division
PRESCALER[7:0] = n
= 0,1,3,5
t(CK)/2
-
t(CK)/2+1
ns
tw(CKL)
t(CK)/2–1
-
t(CK)/2
tw(CKH)
OCTOSPI clock high and low
time, odd division
PRESCALER[7:0] = n
= 2,4,6,8
(n/2)*t(CK)/
(n+1)
-
(n/2)*t(CK)/
(n+1)+1
tw(CKL)
(n/2+1)*t(CK)/
(n+1)–1
-
(n/2+1)*t(CK)
/(n+1)
ts(IN)(3)
Data input setup time
-
3.0
-
-
th(IN)(3)
Data input hold time
-
1.5
-
-
tv(OUT)
Data output valid time
-
-
0.5
1(4)
th(OUT)
Data output hold time
-
0
-
-
1. All values apply to Octal and Quad-SPI mode.
2. Guaranteed by characterization results.
3. Delay block bypassed.
4. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.
Table 75. OCTOSPI characteristics in SDR mode(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv36878V1
Data output
D0
D1
D2
Clock
Data input
D0
D1
D2
t(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
ts(IN)
th(IN)
tv(OUT)
th(OUT)



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