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EVAL-AD1839EB Fiches technique(PDF) 5 Page - Analog Devices

No de pièce EVAL-AD1839EB
Description  2 ADC, 6 DAC, 96 kHz, 24-Bit sigma-delta Codec
PDF  24 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

EVAL-AD1839EB Fiches technique(HTML) 5 Page - Analog Devices

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REV. B
AD1839
–5–
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
tTBD
BCLK Delay
20
ns
From MCLK Rising
tFSD
FSTDM Delay
5
ns
From BCLK Rising
tTABD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM256 MODE (Slave)
fAB
BCLK Frequency
256
fS
tTBCH
BCLK High
15
ns
tTBCL
BCLK Low
15
ns
tTFS
FSTDM Setup
10
ns
To BCLK Falling
tTFH
FSTDM Hold
10
ns
From BCLK Falling
tTBDD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
AUXILIARY INTERFACE
tAXDS
AAUXDATA Setup
10
ns
To AUXBCLK Rising
tAXDH
AAUXDATA Hold
10
ns
From AUXBCLK Rising
tDXD
DAUXDATA Delay
15
ns
From AUXBCLK Falling
fABP
AUXBCLK Frequency
64
fS
Slave Mode
tAXBH
AUXBCLK High
15
ns
tAXBL
AUXBCLK Low
15
ns
tAXLS
AUXLRCLK Setup
10
ns
To AUXBCLK Rising
tAXLH
AUXLRCLK Hold
10
ns
From AUXBCLK Rising
Master Mode
tAUXLRCLK
AUXLRCLK Delay
5
ns
From AUXBCLK Falling
tAUXBCLK
AUXBCLK Delay
15
ns
From MCLK Rising
Specifications subject to change without notice.
MCLK
t
MH
PD/RST
t
ML
t
PDR
t
MCLK
Figure 1. MCLK and
PD/RST Timing



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