PSD813F1V datasheet(90/110 Pages) STMICROELECTRONICS

90 / 110 page

PSD813F1V

90/110

Table 56. READ Timing (3V devices)

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD and PSEN have the same timing for 8031.

3. Any input used to select an internal PSD function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS, LDS, and UDS signals.

6. In Turbo Off mode, add 20ns to tAVQV.

Symbol

Parameter

Conditions

-15

-20

Turbo

Off

Unit

Min

Max

Min

Max

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 3)

tLXAX

Address Hold Time

(Note 3)

tAVQV

Address Valid to Data Valid

(Note 3,6)

150

200

+ 20

tSLQV

CS Valid to Data Valid

150

200

tRLQV

RD to Data Valid 8-Bit Bus

(Note 5)

RD or PSEN to Data Valid 8-Bit Bus,

8031, 80251

(Note 2)

tRHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width (also DS, LDS, UDS)40

RD or PSEN Pulse Width (8031, 80251)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time to Enable

tELTL

R/W Hold Time After Enable

tAVPV

Address Input Valid to

Address Output Delay

(Note 4)

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