2

Integrated

Circuit

Systems, Inc.

ICS9DB102

0852C—09/12/05

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

PLL_BW

IN

3.3V input for selecting PLL Band Width

0 = low, 1= high

2

CLK_INT

IN

"True" reference clock input.

3

CLK_INC

IN

"Complementary" reference clock input.

4

**CLKREQ0#

IN

Output enable for SRC/PCI Express output pair '0'

0 = enabled, 1 = tri-stated

5

VDD

PWR

Power supply, nominal 3.3V

6

GND

PWR

Ground pin.

7

PCIEXT0

OUT

True clock of differential PCI_Express pair.

8

PCIEXC0

OUT

Complement clock of differential PCI_Express pair.

9

VDD

PWR

Power supply, nominal 3.3V

10

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

11

SMBCLK

IN

Clock pin of SMBUS circuitry, 5V tolerant

12

VDD

PWR

Power supply, nominal 3.3V

13

PCIEXC1

OUT

Complement clock of differential PCI_Express pair.

14

PCIEXT1

OUT

True clock of differential PCI_Express pair.

15

GND

PWR

Ground pin.

16

VDD

PWR

Power supply, nominal 3.3V

17

**CLKREQ1#

IN

Output enable for SRC/PCI Express output pair '1'

0 = enabled, 1 = tri-stated

18

IREF

OUT

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

19

GNDA

PWR

Ground pin for the PLL core.

20

VDDA

PWR

3.3V power for the PLL core.

Pins preceeded by '**' have internal 120K ohm pull down resistors

Note: