PRT2011CVL5A datasheet(44/112 Pages) NXP

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i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Electrical Characteristics

Figure 15 shows the output timing in ASYNC mode.

Figure 15. SEMC output timing in ASYNC mode

4.5.1.1.2

SEMC output timing in SYNC mode

Table 33 shows SEMC output timing in SYNC mode.

2 ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N,

TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about

SEMC_*CR0.AS register field.

3 Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set

with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more

detail about SEMC_*CR0.WEH register field.

4 WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value

N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail

about SEMC_*CR0.WEL register field.

Table 33. SEMC output timing in SYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

—

166

MHz

—

TCK

Internal clock period

—

TDVO

Data output valid time

—

These timing parameters apply to

Address/Data/DM/CKE/control

signals with SEMC_CLK for

SDRAM.

TDHO

Data output hold time

-1

—

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