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M24128X-FCU6T/TF Fiches technique(PDF) 14 Page - STMicroelectronics

No de pièce M24128X-FCU6T/TF
Description  128-Kbit serial I²C bus EEPROM with configurable device address and software write protection, delivered in 4-ball CSP
PDF  35 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24128X-FCU6T/TF Fiches technique(HTML) 14 Page - STMicroelectronics

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6.3
Read operations on memory array
Read operations are performed independently of the state of the software write protect bit (SWP).
After the successful completion of a read operation, the device internal address counter is incremented by one, to
point to the next byte address.
For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in)
during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data
transfer and switches to its Standby mode.
Figure 9. Read mode sequences
Dev sel *
Byte addr
Byte addr
Dev sel
Data out 1
Data out N
Current
Address
Read
Dev sel
Data out
Random
Address
Read
Dev sel *
Data out
Sequential
Current
Read
Data out N
Dev sel *
Byte addr
Byte addr
Sequential
Random
Read
Dev sel *
Data out1
ACK
RW
NO ACK
ACK
RW
ACK
ACK
ACK
RW
ACK
ACK
ACK
NO ACK
RW
NO ACK
ACK
ACK
ACK
RW
ACK
ACK
RW
ACK
NO ACK
M24128X-FCU
Read operations on memory array
DS12680 - Rev 2
page 14/35



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