May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

2 of 14

Notice: The information in this document is subject to change without notice.

Block Diagram

Pin Configuration

Table 1. Function Table

Control

Default

0

1

CLK_SEL

1

CLK0 input selected

CLK1 input selected

OE

1

Outputs disabled (high–impedance state)

1

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

Note: 1. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP

Table 2. Pin Configuration

Pin #

Pin Name

I/O

Type

Function

3

CCLK0

Input

LVCMOS

Clock signal input

4

CCLK1

Input

LVCMOS

Alternative clock signal input

2

CLK_SEL

Input

LVCMOS

Clock input select

5

CLK_STOP

Input

LVCMOS

Clock output enable/disable

6

OE

Input

LVCMOS

Output enable/disable

(high–impedance tristate)

11,13,15,19,21,23,26,28,30

Q0 – Q8

Output

LVCMOS

Clock outputs

1,8,9,12,16,17,20,24,25,29,32

GND

Supply

Ground

Negative power supply (GND) for

Output and Core

7,10,14,18,22,27,31

Supply

Positive power supply for I/O and

to the positive power supply for

correct operation

Q0

Q1

CLK

CCLK0

Q2

Q3

Q4

STOP

0

1

CCLK1

CLK_SEL

SYNC

CLK_STOP

Q5

Q5

Q6

Q7

OE

(All input resistors have a value of 25KΩ)

GND

Q2

Q1

GND

Q0

GND

GND

25

24

26

27

28

29

30

31

32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Q6

Q7

GND

Q8

GND

ASM2I99447