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AS7C33512PFS18A Fiches technique(PDF) 12 Page - Alliance Semiconductor Corporation

No de pièce AS7C33512PFS18A
Description  3.3V 512K x 18 pipeline burst synchronous SRAM
PDF  20 Pages
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Fabricant  ALSC [Alliance Semiconductor Corporation]
Site Internet  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C33512PFS18A Fiches technique(HTML) 12 Page - Alliance Semiconductor Corporation

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®
AS7C33512PFS18A
11/30/04; v.2.2
Alliance Semiconductor
12 of 20
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
don’t care
Falling input
Rising input
Undefined
CE1
tCYC
tCH
tCL
tADSPS
tADSPH
tAS
tAH
tWS
tADVS
tOH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
Dout
tCSS
tHZC
tCD
tWH
tADVH
tHZOE
tADSCS
tADSCH
LOAD NEW ADDRESS
ADV inserts wait states
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2)
Q(A2Ý01)
Q(A3Ý01)
Q(A3Ý10)
Q(A1)
A2
A1
A3
tOE
tLZOE
tCSH
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Burst
Read
Q(A 2Ý01)
Read
Q(A3)
DSEL
Burst
Read
Q(A 2Ý10)
Suspend
Read
Q(A 2Ý10)
Burst
Read
Q(A 2Ý11)
Burst
Read
Q(A 3Ý01)
Burst
Read
Q(A 3Ý10)
Burst
Read
Q(A 3Ý11)



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