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RM48L540DPGET Fiches technique(PDF) 83 Page - Texas Instruments |
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RM48L540DPGET Fiches technique(HTML) 83 Page - Texas Instruments |
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83 / 174 page ![]() RM48L940, RM48L740, RM48L540 www.ti.com SPNS175C – APRIL 2012 – REVISED JUNE 2015 The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM. NOTE The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 83 Submit Documentation Feedback |
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