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IS25LP032D-RBLA3 Fiches technique(PDF) 81 Page - Integrated Silicon Solution, Inc

No de pièce IS25LP032D-RBLA3
Description  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  118 Pages
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Fabricant  ISSI [Integrated Silicon Solution, Inc]
Site Internet  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP032D-RBLA3 Fiches technique(HTML) 81 Page - Integrated Silicon Solution, Inc

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IS25LP032D
IS25WP032D
Integrated Silicon Solution, Inc.- www.issi.com
81
Rev. A12
08/04/2020
8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device  Send IRER instruction code  Send three
address bytes  Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE# is pulled
high, Erase operation will begin immediately. The internal control logic automatically handles the erase voltage and
timing.
Figure 8.60 IRER (Information Row Erase) Sequence
Instruction = 64h
23
CE #
SCK
SI
3
2
SO
1
0
3-byte Address
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
Mode 3
Mode 0



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