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LP5302 Fiches technique(PDF) 2 Page - Lowpower Semiconductor inc |
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LP5302 Fiches technique(HTML) 2 Page - Lowpower Semiconductor inc |
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2 / 7 page ![]() LP5302-01 Sep.-2017 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 2 of 7 Preliminary Datasheet LP5302 Functional Pin Description VOUT GND EN VIN NC 1 2 3 4 6 Top View DRIVER 5 Pin Description PIN Name Description 1 EN Chip enable pin. Active low. 2 GND Ground. 3 VIN Input pin. A 1μF low ESR ceramic capacitor or larger must be connected as close as to this pin. It is recommended to use 50V capacitor or according to application. 4 VOUT Output pin. 5 DRIVER External NMOS gate driver. It must be floating if the application does not use external NMOS. 6 NC No connection. Function Diagram DRVIER EN |
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