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LP4059 Fiches technique(PDF) 7 Page - Lowpower Semiconductor inc |
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LP4059 Fiches technique(HTML) 7 Page - Lowpower Semiconductor inc |
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7 / 9 page ![]() LP4059-00 Jan.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 7 of 9 Preliminary Datasheet LP4059 Layout Considerations For the main current paths as indicated in bold lines, keep their traces short and wide. Put the input and output capacitor as close as possible to the device pins (VCC, BAT and GND). Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors |
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