19/23

M41T00S

Figure 15. Bus Timing Requirements Sequence

Table 11. AC Characteristics

2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.

Sym

Min

Typ

Max

Units

SCL Clock Frequency

0

400

kHz

Clock Low Period

1.3

µs

Clock High Period

600

ns

SDA and SCL Rise Time

300

ns

SDA and SCL Fall Time

300

ns

START Condition Hold Time

(after this period the first clock pulse is generated)

600

ns

START Condition Setup Time

(only relevant for a repeated start condition)

600

ns

(2)

Data Setup Time

100

ns

Data Hold Time

0

µs

STOP Condition Setup Time

600

ns

Time the bus must be free before a new

transmission can start

1.3

µs

AI00589

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P