 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
ADC3541 Fiches technique(PDF) 13 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADC3541 Fiches technique(HTML) 13 Page - Texas Instruments |
|
|
13 / 68 page  PARAMETER TEST CONDITIONS MIN NOM MAX UNIT OUTPUT RATE: 10 MSPS tPD Propagation delay: sampling clock falling edge to DCLK rising edge SDR CMOS TBD 6.3 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge DDR CMOS TBD 6.3 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge Serial CMOS: 2-wire TBD 2.0 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge Serial CMOS: 1-wire TBD 2.0 ns tCD DCLK rising edge to output data delay TBD 0.2 OUTPUT RATE: 25 MSPS tPD Propagation delay: sampling clock falling edge to DCLK rising edge SDR CMOS TBD 6.2 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge DDR CMOS TBD 6.2 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge Serial CMOS: 2-wire TBD 2.0 ns tCD DCLK rising edge to output data delay TBD 0.2 OUTPUT RATE: 65 MSPS tPD Propagation delay: sampling clock falling edge to DCLK rising edge SDR CMOS TBD 6.1 ns tCD DCLK rising edge to output data delay TBD 0.2 tPD Propagation delay: sampling clock falling edge to DCLK rising edge DDR CMOS TBD 6.1 ns tCD DCLK rising edge to output data delay TBD 0.2 SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input fCLK(SCLK) Serial clock frequency 10 12 MHz tSU(SEN) SEN to rising edge of SCLK TBD ns tH(SEN) SEN from rising edge of SCLK TBD ns tSU(SDIO) SDIO to rising edge of SCLK TBD ns tH(SDIO) SDIO from rising edge of SCLK TBD ns SERIAL PROGRAMMING INTERFACE (SDIO) - Output t(OZD) SDIO tri-state to driven TBD ns t(ODZ) SDIO data to tri-state TBD ns t(OD) SDIO valid from falling edge of SCLK TBD ns www.ti.com ADC3541 SBAS840 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADC3541 |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
