XRT83SL34 datasheet(67/80 Pages) EXAR

67 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

MCLKRATE

Master clock Rate Select: The state of this bit programs the

Master Clock Synthesizer to generate the T1/J1 or E1 clock.

The Master Clock Synthesizer will generate the E1 clock when

MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =

“1”.

R/W

RXMUTE

Receive Output Mute: Writing a “1” to this bit, mutes receive

outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for

any channel that detects an RLOS condition.

NOTE: RCLK is not muted.

R/W

EXLOS

Extended LOS: Writing a “1” to this bit extends the number of

zeros at the receive input of each channel before RLOS is

declared to 4096 bits. Writing a “0” reverts to the normal mode

(175+75 bits for T1 and 32 bits for E1).

R/W

ICT

In-Circuit-Testing: Writing a “1” to this bit configures all the

output pins of the chip in high impedance mode for In-Circuit-

Testing. Setting the ICT bit to “1” is equivalent to connecting

the Hardware ICT pin 88 to ground.

R/W

TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION

1000010

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

GAUGE1

Wire Gauge Selector Bit 1:

This bit together with bit D6 are used to select wire gauge size

as shown in the table below.

R/W

GAUGE0

Wire Gauge Selector Bit 0:

See bit D7.

R/W

TXONCNTL

Transmit On Control:

In Host mode, setting this bit to “1” transfers the control of the

Transmit On/Off function to the TXON_n Hardware control

pins.

NOTE: This provides a faster On/Off capability for redundancy

application.

R/W

TERCNTL

Termination Control.

In Host mode, setting this bit to “1” transfers the control of the

RXTSEL to the RXTSEL Hardware control pin.

NOTE: This provides a faster On/Off capability for redundancy

application.

R/W

TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION

GAUGE1

GAUGE0

Wire Size

22 and 24 Gauge

26 Gauge

24 Gauge

22 Gauge

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