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SN74HCS05DR Fiches technique(PDF) 6 Page - Texas Instruments |
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SN74HCS05DR Fiches technique(HTML) 6 Page - Texas Instruments |
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6 / 15 page ![]() Input 50% VOH VOL tPLZ (1) tPZL (2) VOH VOL tPZL (2) tPLZ (1) 50% 50% 50% VCC 0 V 10% VCC Output Output 10% VOH VOL Output VCC 0 V Input tf (1) tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% CL (1) RL From Output Under Test VCC Test Point S1 6 SN74HCS05 SCLS797 – JUNE 2020 www.ti.com Product Folder Links: SN74HCS05 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Parameter Measurement Information (continued) CL= 50 pF and includes probe and jig capacitance. Figure 4. Load Circuit Figure 5. Voltage Waveforms Transition Times The maximum between tPLH and tPHL is used for tpd. Figure 6. Voltage Waveforms Propagation Delays |
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