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80C286/883 Fiches technique(PDF) 10 Page - Intersil Corporation

No de pièce 80C286/883
Description  High Performance Microprocessor with Memory Management and Protection
PDF  13 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

80C286/883 Fiches technique(HTML) 10 Page - Intersil Corporation

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137
80C286/883
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat
φ1 of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
Waveforms (Continued)
φ2
BUS CYCLE TYPE
VCH
VCL
CLK
φ1
PCLK
(SEE NOTE 1)
TX
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
ERROR, BUSY
(SEE NOTE 2)
19
19
4
5
5
4
φ2
7
RESET
φ1
φ1
φ2
6
VCH
VCL
CLK
(SEE NOTE 1)
TX
VCH
CLK
VCL
RESET
TX
φ2
φ2
φ1
7
6
(SEE NOTE 1)



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