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DF2B6M4ASL Fiches technique(PDF) 2 Page - Toshiba Semiconductor

No de pièce DF2B6M4ASL
Description  ESD Protection Diodes Silicon Epitaxial Planar
PDF  9 Pages
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

DF2B6M4ASL Fiches technique(HTML) 2 Page - Toshiba Semiconductor

  DF2B6M4ASL Datasheet HTML 1Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 2Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 3Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 4Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 5Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 6Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 7Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 8Page - Toshiba Semiconductor DF2B6M4ASL Datasheet HTML 9Page - Toshiba Semiconductor  
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DF2B6M4ASL
2
5.
5.
5.
5. Example of Circuit Diagram
Example of Circuit Diagram
Example of Circuit Diagram
Example of Circuit Diagram
6.
6.
6.
6. Quick Reference Data
Quick Reference Data
Quick Reference Data
Quick Reference Data
Characteristics
Working peak reverse voltage
Total capacitance
Dynamic resistance
Electrostatic discharge voltage
(IEC61000-4-2) (Contact)
Symbol
VRWM
Ct
RDYN
VESD
Note
(Note 1)
(Note 2)
(Note 3)
Test Condition
VR = 0 V, f = 1 MHz
Min
Typ.
0.15
0.7
Max
5.5
0.2
15
Unit
V
pF
kV
Note 1: Recommended operating condition.
Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A.
Note 3: Criterion: No damage to devices.
2019-08-05
Rev.1.0
©2019
Toshiba Electronic Devices & Storage Corporation



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