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AM652X Fiches technique(PDF) 146 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 146 Page - Texas Instruments |
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146 / 277 page ![]() BC1 PORz BOOTMODE[18:00] BC2 BC3 MCU_PORz MCU_BOOTMODE[09:00] B 4 C 146 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Table 5-19. Boot Configuration Timing Requirements (continued) NO. PARAMETER MIN MAX UNIT BC4 th(MCU_PORz - MCU_BOOTMODE) Hold time, All Bootmode pins active after MCU_PORz inactive (high) 0 ns Figure 5-8. Boot Configuration Timing 5.9.4 Clock Specifications 5.9.4.1 Input Clocks / Oscillators Various external clock inputs are needed to drive the device. Summary of these input clock signals are: • OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs. • WKUP_OSC0_XO/WKUP_OSC0_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MCU domain and MAIN domain. • WKUP_LFOSC_XO/WKUP_LFOSC_XI — External main crystal interface pins connected to internal oscillator which sources reference clock provides a clock for low power operation in deeper sleep modes. • MCU_EXT_REFCLK0 — Optional external system clock input (MCU domain). • EXT_REFCLK1— Optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and MCASP can be sourced by EXT_REFCLK1 (sourced externally). • SERDES0_REFCLK P/N and SERDES1_REFCLK P/N — SerDes reference clock for PCIe or Optional USB3.0 PHY. • MCU_CPTS0_RFT_CLK — CPTS reference clock inputs for MCU_CPTS0_RFT_CLK. • CPTS_RFT0_CLK — CPTS reference clock inputs for CPTS0_RFT_CLK. • VOUT1_EXTPCLKIN — Optional for the DPI1 Port of DSS. • REFCLK0 P/N and REFCLK1 P/N — There are 2 differential clock output pins to support 2 PCIe devices. Figure 5-9 shows the external input clock sources to peripherals. |
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