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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 229 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 229 Page - Texas Instruments |
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229 / 277 page  EDC_LATCHx_IN PRLA2 SPRSP08_TIMING_PRU_IEP_02 PRLA1 EDIO_DATA_OUT SPRSP08_TIMING_PRU_EDIO_DATA_OUT IEPIO4 EDC_SYNCx_OUT PRIEP4 PRIEP2 PRIEP3 EDIO_DATA_IN[7:0] SPRSP08_TIMING_PRU_IEP_01 PRIEP1 229 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated (1) P = PRU-ICSS IEP clock source period. Figure 5-104. PRU_ICSSG PRU IEP SYNCx Timing Table 5-99. PRU_ICSSG IEP Timing Requirements - Digital IOs NO. PARAMETER DESCRIPTION MIN MAX UNIT IEPIO1 tw(EDIO_OUTVALIDL) Pulse Duration, EDIO_OUTVALID Low -2+14×P (1) ns IEPIO2 tw(EDIO_OUTVALIDH) Pulse Duration, EDIO_OUTVALID High -2+32×P (1) ns IEPIO3 td(EDIO_OUTVALID- EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0 0+18×P (1) ns IEPIO4 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 5 ns (1) P = PRU-ICSS IEP clock source period. Figure 5-105. PRU_ICSSG PRU IEP Digital IOs Timing Table 5-100. PRU_ICSSG IEP Timing Requirements - LATCHx_IN NO. PARAMETER DESCRIPTION MIN MAX UNIT PRLA1 tw(EDC_LATCHx_INL) Pulse Duration, EDC_LATCHx_IN Low 2+3×P (1) ns PRLA2 tw(EDC_LATCHx_INH) Pulse Duration, EDC_LATCHx_IN High 2+3×P (1) ns (1) P = PRU-ICSS IEP clock source period. Figure 5-106. PRU_ICSSG PRU IEP LATCHx_IN Timing 5.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART) 5.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing |
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