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AM652X Fiches technique(PDF) 166 Page - Texas Instruments

No de pièce AM652X
Description  Processors Silicon Revision 1.0
PDF  277 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

AM652X Fiches technique(HTML) 166 Page - Texas Instruments

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VOUT1_PCLK
VOUT1_VSYNC
VOUT1_HSYNC
VOUT1_DATA[23:0]
VOUT1_DE
data_1 data_2
data_n
D1
D2
D3
D5
D5
D4
D5
DPI_01
VOUT1_PCLK
Falling-edge Clock Reference
Rising-edge Clock Reference
166
AM6548, AM6528, AM6546
AM6526, AM6527
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Specifications
Copyright © 2017–2019, Texas Instruments Incorporated
5.9.5.5
DSS
For more details about features and additional description information on the device Display Subsystem –
Video Output Ports, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
Table 5-42, Table 5-43, Figure 5-35 and Figure 5-36 assume testing over the recommended operating
conditions and electrical characteristic conditions.
Table 5-42. DPI Video Output Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
D1
tc(VOUT1_PCLK)
Cycle time, VOUT1_PCLK
6.06
ns
D2
tw(VOUT1_PCLKL)
Pulse duration, VOUT1_PCLK low
0.45 ×
P(1)
ns
D3
tw(VOUT1_PCLKH)
Pulse duration, VOUT1_PCLK high
0.45 ×
P(1)
ns
D4
td(VOUT1_PCLK-
VOUT_DATA)
Delay time, VOUT1_PCLK to VOUT1_DATA[23:0]
-0.68
1.78
ns
D5
td(VOUT1_PCLK-
VOUT_CTRL)
Delay time, VOUT1_PCLK to VOUT1_VSYNC, VOUT1_HSYNC,
VOUT1_DE
-0.68
1.78
ns
(1) P = output VOUT1_PCLK period in ns.
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of VOUT1_HSYNC and VOUT1_VSYNC are programmable, refer to section Display Subsystem (DSS)
in the device TRM.
(3) The VOUT1_PCLK frequency can be configured, refer to section Display Subsystem (DSS) in the device TRM..
Figure 5-35. DPI Video Output (1)(2)(3)



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