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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 164 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 164 Page - Texas Instruments |
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164 / 277 page  RGMII[x]_TXC (A) RGMII[x]_TXD[3:0] (B) RGMII[x] TCTL _ (B) RGMII5 1st Half-byte TXERR TXEN 2nd Half-byte RGMII4 RGMII4 RGMII2 RGMII3 RGMII1 RGMII5 SPRSP08_CPSW2G_RGMIITX 164 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Table 5-39, Table 5-40, and Figure 5-33 present switching characteristics for transmit - RGMII for 10 Mbps, 100 Mbps, and 1000 Mbps. Table 5-39. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII1 tc(TXC) Cycle time, TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(TXCH) Pulse duration, TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(TXCL) Pulse duration, TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII4 tt(TXC) Transition time, TXC 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns Table 5-40. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII5 tsk(TD-TXC) TD to TXC output skew 10Mbps - 0.81 0.81 ns 100Mbps - 0.81 0.81 ns 1000Mbps - 0.81 0.81 ns tsk(TX_CTL-TXC) TX_CTL to TXC output skew 10Mbps - 0.81 0.81 ns 100Mbps - 0.81 0.81 ns 1000Mbps - 0.81 0.81 ns RGMII6 tt(TD) Transition time, TD 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns tt(TX_CTL) Transition time, TX_CTL 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 5-33. CPSW2G Transmit Interface Timing RGMII Mode |
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