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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7FDALIF2M6 Fiches technique(PDF) 74 Page - STMicroelectronics |
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ST7FDALIF2M6 Fiches technique(HTML) 74 Page - STMicroelectronics |
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74 / 141 page  ST7DALI 74/141 DALI COMMUNICATION MODULE (Cont’d) 11.4.10 Bi-phase Bit Detection The clock used for sampling the DALI signal is pro- grammed by the DCMCLK register. Each bit phase is sampled 16 times. The bit phase level is determined by two of three sample clock pulses (pulses 6,7,8). The two phase levels of the bi- phase bit are shifted into the 4-bit pre-shift register at the 9th sample clock pulse. Only the second phase level of the bi-phase bit is shifted into the 16-bit shifter. The 4-bit pre-shifter is used to detect any errors in the received frame. When a change of phase is detected (edge trig- ger), the 4-bit sample clock counter (integer range 0 to15) is cleared. Figure 43. DALI Signal Sampling DALI Signal 12 3456 78910 11 12 13 14 15 1234 56789 10 11 12 13 14 15 Phase Detector Shifter Clock Edge Trigger 4-bit Pre-shifter 001 x 4-bit sample clock counter 16-bit Shifter xxxx xxx1 1 |
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